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| ? 2004 microchip technology inc. ds21730d-page 1 mcp201 features ? supports baud rates up to 20 kbaud 40v load dump protected wide supply voltage, 6.0 ? 18.0v, continuous - maximum input voltage of 30v extended temperature range: -40c to +125c interface to standard usarts compatible with lin spec 1.3 local interconnect network (lin) line pin: - internal pull-up resistor and diode - protected against ground shorts (lin pin to ground) - protected against lin pin loss of ground - high current drive, 40 ma i ol 200 ma automatic thermal shutdown on-board voltage regulator: - output voltage of 5v with 5% tolerances over temperature range - maximum output current of 50 ma - able to drive an external series-pass transistor for increased current supply capability - internal thermal overload protection - internal short-circuit current limit - external components limited to filter capacitor only and load capacitor package types block diagram mcp201 pdip, soic, dfn 8 7 6 5 1 2 3 4 rxd cs/wake v reg txd fault /slps v bat lin v ss voltage regulator ratiometric reference oc thermal protection internal circuits v reg fault /slps rxd txd v bat lin vss approx. cs/wake wake-up logic slope control por 30 k ? lin transceiver with voltage regulator
mcp201 ds21730d-page 2 ? 2004 microchip technology inc. notes: ? 2004 microchip technology inc. ds21730d-page 3 mcp201 1.0 device overview the mcp201 provides a physical interface between a microcontroller and a lin half-duplex bus. it is intended for automotive and industrial applications with serial bus speeds up to 20 kbaud. the mcp201 provides a half-duplex, bidirectional communications interface between a microcontroller and the serial network bus. this device will translate the cmos/ttl logic levels to lin level logic, and vice versa. the lin specification 1.3 requires that the transceiver of all nodes in the system be connected via the lin pin, referenced to ground and with a maximum external termination resistance of 510 ? from lin bus to battery supply. the 510 ? corresponds to 1 master and 16 slave nodes. the mcp201 provides a +5v 50 ma regulated power output. the regulator uses a ldo design, is short- circuit-protected and will turn the regulator output off if it falls below 3.5v. the mcp201 also includes thermal shutdown protection. the regulator has been specifi- cally designed to operate in the automotive environ- ment and will survive reverse battery connections, +40v load dump transients and double-battery jumps (see section 1.6 ?internal voltage regulator? ). 1.1 optional external protection 1.1.1 transient voltage protection (load dump) an external 27v transient suppressor (tvs) diode, between v bat and ground, with a 50 ? resistor in series with the battery supply and the v bat pin serve to protect the device from power transients (see figure 1-2) and esd events. while this protection is optional, it should be considered as good engineering practice. 1.1.2 reverse battery protection an external reverse-battery-blocking diode can be used to provide polarity protection (see figure 1-2). this protection is optional, but should be considered as good engineering practice. 1.2 internal protection 1.2.1 esd protection for component-level esd ratings, please refer to the maximum operation specifications. 1.2.2 ground loss protection the lin bus specification states that the lin pin must transition to the recessive state when ground is disconnected. therefore, a loss of ground effectively forces the lin line to a hi-impedance level. 1.2.3 thermal protection the thermal protection circuit monitors the die temperature and is able to shut down the lin transmitter and voltage regulator. refer to table 1-1 for details. there are three causes for a thermal overload. a thermal shut down can be triggered by any one, or a combination of, the following thermal overload conditions. voltage regulator overload lin bus output overload increase in die temperature due to increase in environment temperature driving the txd and checking the rxd pin makes it possible to determine whether there is a bus contention (rx = low, tx = high) or a thermal overload condition (rx = high, tx = low). table 1-1: sources of thermal overload note: after recovering from a thermal, bus or voltage regulator overload condition, the device will be in the ready1 mode. in order to go into operational mode, cs/wake pin has to be toggled. txd rxd comments l h lin transmitter shutdown, receiver and voltage regulator active, thermal overload condition. h l regulator shutdown, receiver active, bus contention. legend: x = don?t care, l = low, h = high note 1: lin transceiver overload current on the lin pin is 200 ma. 2: voltage regulator overload current on voltage regulator greater than 50 ma. mcp201 ds21730d-page 4 ? 2004 microchip technology inc. 1.3 modes of operation for an overview of all operational modes, please refer to table 1-2. 1.3.1 power-down mode in the power-down mode, the transmitter and the voltage regulator are both off. only the receiver section and the cs/wake pin wake-up circuits are in operation. this is the lowest power mode. if any bus activity (e.g., a break character) should occur during power-down mode, the device will immediately enable the voltage regulator. once the output has stabilized, the device will enter ready mode. the part will enter the operation mode, if the cs/wake pin should become active-high (? 1 ?). 1.3.2 ready and ready1 modes there are two states for the ready mode. the only difference between these states is the transition during start-up. the state ready1 mode ensures that the transition from ready to operation mode (once a rising edge of cs/wake) occurs without disrupting bus traffic. immediately upon entering either ready1 or ready mode, the voltage regulator will turn on and provide power. the transmitter portion of the circuit is off, with all other circuits (including the receiver) of the mcp201 being fully operational. the lin pin is kept in a recessive state. if a microcontroller is being driven by the voltage regulator output, it will go through a power-on reset and initialization sequence. all other circuits, other than the transmitter, are fully operational. the lin pin is held in the recessive state. the device will stay in ready mode until the cs/wake pin transitions high (? 1 ?). after cs/wake is active, the transmitter is enabled and the device enters operation mode. the device may only enter power-down mode after going through the operation mode step. at power-on of the v bat supply pin, the component is in either ready or ready1 mode, waiting for a cs/wake rising edge. the mcp201 will stay in either mode for 600 s as the regulator powers its internal circuitry and waits until the cs/wake pin transitions high. during the 600 s delay, the mcp201 will not recognize a cs/wake event. the cs/wake transition from low to high should not occur until after this delay. 1.3.3 operation mode in this mode, all internal modules are operational. the mcp201 will go into power-down mode on the falling edge of cs/wake. figure 1-1: operational modes state diagrams note: while the mcp201 is in shutdown, txd should not be actively driven high. if txd is driven high actively, it may power internal logic. operation mode power-down mode ready mode bus activity cs/wake = true cs/wake = true por cs/wake = false ready1 mode cs/wake = true cs/wake = false cs/wake = false start f l t f l t ? 2004 microchip technology inc. ds21730d-page 5 mcp201 table 1-2: overview of operational modes 1.4 typical applications figure 1-2: typical mcp201 application state transmitter voltage regulator operation comments por off off read cs/wake. if low, then ready. if high, ready1 mode. sample fault/slps and select slope ready off on if cs/wake rising edge, then operation mode. bus off state ready1 off on if cs/wake falling edge, then ready mode. bus off state operation on on if cs/wake falling edge, then power down. normal operation mode power-down off off on lin bus falling, go to ready mode. on cs/wake rising edge, go to operational mode low-power mode lin bus d2 (4) v bat lin v reg txd rxd v ss v dd v ss txd rxd +5v picmicro ? +12v 10 uf c g cs/wake i/o fault /slps i/o 27v 1k ? +12v master node only +12v 10 k ? wake-up v reg or v ss 100 k ? optional components (5) optional components mcp201 c f d1 (3) note 1: c g is the load capacitor should be ceramic or tantalum for extended temperatures, 5-22 f with esr 0.4 ? - 5 ? . . 2: c f if the filter capacitor for the external voltage supply. 3: this diode is only needed if cs/wake is connected to 12v supply. 4: transient suppressor diode. vclamp l = 40v. 5: these components are for load dump protection. 24v mcu mcp201 ds21730d-page 6 ? 2004 microchip technology inc. figure 1-3: typical lin network configuration lin bus mcp201 master c 1k ? v bat slave 1 c slave 2 c slave n <16 c 40m + return lin bus lin bus mcp201 lin bus mcp201 lin bus mcp201 ? 2004 microchip technology inc. ds21730d-page 7 mcp201 1.5 pin descriptions table 1-3: mcp201 pinout overview 1.5.1 receive data output (rxd) the receive data output pin is a standard cmos output and follows the state of the lin pin. the lin receiver monitors the state of the lin pin and generates the output signal rxd. 1.5.2 cs/wake chip select input pin. this pin controls whether the part goes into ready1 or ready mode at power-up. the internal pull-down resistor will keep the cs/wake pin low. this is done to ensure that no disruptive data will be present on the bus while the microcontroller is executing a power-on reset and i/o initialization sequence. the pin must see a low-to-high transition to activate the transmitter. after cs/wake transitions to ' 1 ', the transmitter is enabled. if cs/wake = ' 0 ', the device is in ready1 mode on power-up or in low-power mode. in low- power mode, the voltage regulator is shut down, the transmitter driver is disabled and the receiver logic is enabled. an external switch (see figure 1-2) can then wake up both the transceiver and the microcontroller. an external-blocking diode and current-limiting resistor are necessary to protect the microcontroller i/o pin. 1.5.3 power output (v reg ) positive supply voltage regulator output pin. 1.5.4 transmit data input (txd) the transmit data input pin has an internal pull-up to v reg . the lin pin is low (dominant) when txd is low, and high (recessive) when txd is high. in case the thermal protection detects an over-temper- ature condition while the signal txd is low, the transmitter is shutdown. the recovery from the thermal shutdown is equal to adequate cooling time. 1.5.5 ground (v ss ) ground pin. 1.5.6 lin the bidirectional lin bus interface pin is the driver unit for the lin pin and is controlled by the signal txd. lin has an open collector output with a current limitation. to reduce emi, the edges during the signal changes are slope-controlled. 1.5.7 battery (v bat ) battery positive supply voltage pin. this pin is also the input for the internal voltage regulator. 1.5.8 fault /slps fault detect output, slope select input. this pin is usually in output mode. its state is defined as shown in table 1-5. the state of this pin is internally sampled during power- on of v bat . once v bat has reached a stable level, (approximately 6 vdc) and v reg is stable at 4.75- 5.25 vdc, the state of this pin selects which slew rate profile to apply to the lin output. it is only during this time that the pin is used as an input (the output driver is off during this time). the slope will stay selected until the next v bat power-off/power-on sequence, regard- less of any power-down, wake-up or sleep events. only a v bat rising state will cause a sampling of the fault /slps pin. the slope selection will be made irrespective of the state of any other pin. the fault /slps pin is connected to either v reg or v ss through a resistor (approximately 100 k ? ) to make the slope selection. this large resistance allows the fault indication function to overdrive the resistor in normal operation mode. if the fault /slps is high (? 1 ?), the normal slope shap- ing is selected (dv/dt = 2 v/s). if fault /slps is low (? 0 ?) during this time, the alternate slope-shaping is selected (dv/dt = 4 v/s). this mode can be used if a user desires to run at a faster slope. this mode is not lin compliant. devices bond pad name function 8-pin pdip/ soic/dfn normal operation 1 rxd receive data output (cmos output) 2 cs/wake chip select (ttl-hv input) 3v reg power output 4 txd transmit data input (ttl) 5v ss ground 6 lin lin bus (bidirectional- hv) 7v bat battery 8fault /slps fault detect output, slope select input legend: ttl = ttl input buffer, hv = high voltage (v bat ) note: on por, the mcp201 enters ready or ready1 mode (see figure 1-1). in order to enter operational mode, the mcp201 has to see one rising edge on cs/wake 600 s after the voltage regulator reaches 5v. mcp201 ds21730d-page 8 ? 2004 microchip technology inc. table 1-4: fault / slps slope selection during por table 1-5: fault / slps truth table 1.6 internal voltage regulator the mcp201 has a low drop-out voltage, positive regulator capable of supplying 5.00 vdc 5% at up to 50 ma of load current over the entire operating temperature range. with a load current of 50 ma, the minimum input-to-output voltage differential required for the output to remain in regulation is typically +0.5v (+1v maximum over the full operating temperature range). quiescent current is less than 1.0 ma, with a full 50 ma load current, when the input-to-output voltage differential is greater than +2v. the regulator requires an external output bypass capacitor for stability. the capacitor should be either ceramic or tantalum for stable operation over the extended temperature range. the compensation capacitor should range from 10 f ? 22 f and have a esr or csr of 0.4 ? ? 5.0 ? . designed for automotive applications, the regulator will protect itself from reverse battery connections, double- battery jumps and up to +40v load dump transients. the voltage regulator has both short-circuit and thermal shutdown protection built-in. regarding the correlation between v bat , v reg and i dd , please refer to figure 1-4 through 1-6. when the input voltage (v bat ) drops below the differential needed to provide stable regulation, the output v reg will track the input down to approximately 3.5v, at which point the regulator will turn off. this will allow microcontrollers with internal por circuits to generate a clean arming of the power-on reset trip point. the mcp201 will then monitor v bat and turn on the regulator when v bat is 6.0v. the device will come up in either ready1 or ready mode and will have to be transitioned to operational mode to re-enable data transmission. in the start phase, v bat must be at least 6.0v (figure 1-4) to initiate operation during power-up. in power-down mode, the v bat monitor will be turned off. the regulator has a thermal shutdown. if the thermal protection circuit detects an overtemperature condition caused by an overcurrent condition (figure 1-6) of the regulator, it will shut down. the regulator has an overload current limiting. during a short-circuit, v reg is monitored. if v reg is lower than 3.5v, the regulator will turn off. after a thermal recovery time, the v reg will be checked again. if there is no short-circuit (v reg > 3.5v), the regulator will be switched back on. the mcp201 will come up in either ready1 or ready mode and will have to be transitioned to operational mode to re-enable data transmission. the accuracy of the voltage regulator, when using a pass transistor, will degrade due to the extra external components needed. all performance characteristics should be evaluated on every design. fault /slps slope shaping hnormal lalternate (1) note 1: this mode does not conform to lin bus specification version 1.3, but might be used for k-line applications. note: this pin is ? 0 ? whenever the internal circuits have detected a short or thermal excursion and have disabled the lin output driver. note: every time tx is toggled, a fault condition will occur for the length of time, depending on the bus load. the fault time is equal to the propagation delay. txd in rxd out lin bus i/o thermal override fault / slps out comments lhv bat off l bus shorted to battery hhv bat off h bus recessive l l gnd off h bus dominant h l gnd off l bus shorted to ground xxv bat on l thermal excursion legend: x = don?t care ? 2004 microchip technology inc. ds21730d-page 9 mcp201 figure 1-4: voltage regulator output on power-on reset note 1: start-up, v bat < 6.0v, regulator off. 2: v bat > 6.0v, regulator on. 3: v bat 5.5v, regulator tracks v bat , regulator will turn off when v reg < 3.5v. 5.5 3.5 3 0 v reg v -------------- - (1) (2) (3) t 0 t 6 2 8 4 v bat v ------------- - mcp201 ds21730d-page 10 ? 2004 microchip technology inc. figure 1-5: voltage regulator output on power dip note 1: voltage regulator on. 2: v reg 5.5v, regulator tracks v bat until v reg < 3.5v. 3: v reg < 3.5v, regulator is off. 4: v reg > 4.0v, voltage regulator tracks v dd , when v reg > 4.0v. 5 3.5 3 0 v reg v -------------- - (1) (2) (3) t 0 t 6 2 8 4 3.5 v bat v ------------- - 12 (4) 4 ? 2004 microchip technology inc. ds21730d-page 11 mcp201 figure 1-6: voltage regulator output on overcurrent situation 1.7 icsp? considerations the following should be considered when the mcp201 is connected to pins supporting in-circuit programming: power used for programming the microcontroller should be supplied from the programmer, not from the mcp201 the mcp201 should be left unpowered the voltage on v reg should not exceed the maximum output voltage of v reg the txd pin should not be brought high during programming note 1: i reg less than 50 ma, regulator on. 2: after i reg exceeds i reg max, voltage regulator output will be reduced until v reg off is reached. 5 3.5 3 0 v reg v -------------- - (1) (2) t 0 t 50 6 i reg ma ------------ - mcp201 ds21730d-page 12 ? 2004 microchip technology inc. notes: ? 2004 microchip technology inc. ds21730d-page 13 mcp201 2.0 electrical characteristics 2.1 absolute maximum ratings? v in dc voltage on logic pins except cs/wake ................................................................................. -0.3 t o v reg +0.3v v in dc voltage on cs/wake ......................................................................................................... ......-0.3 to v bat +0.3v v bat battery voltage, non-operating (lin bus recessive, no regulator load, t < 60s)....................................-0.3 to +40v v bat battery voltage, transient ( note 1 )........................................................................................................-0.3 to +40v v bat battery voltage, continuous ................................................................................................... ...............-0.3 to +30v v lbus bus voltage, continuous....................................................................................................... ................-18 to +30v v lbus bus voltage, transient ( note 1 )............................................................................................................-27 to +40v i lbus bus short circuit current limit ............................................................................................... .....................200 ma esd protection on lin, v bat (human body model) ( note 2 ) .................................................................................. >4 kv esd protection on all other pins (human body model) ( note 2 ) ............................................................................. >2 kv maximum junction temperature ................................................................................................... .......................... 150 c storage temperature ............................................................................................................ ...................... -55 to +150 c note 1: iso 7637/1 load dump compliant (t < 500 ms). 2: according to jesd22-a114-b. ? notice : stresses above those listed under ?maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. mcp201 ds21730d-page 14 ? 2004 microchip technology inc. 2.2 dc specifications dc specifications electrical characteristics: unless otherwise indicated, all limits are specified for: v bat = 6.0v to 18.0v t amb = -40c to +125c c loadreg = 10 f sym. parameter min. typ. max. units conditions power i batq v bat quiescent operating current (voltage regulator without load and transceiver) ? 0.45 1.0 ma i vreg = 0 ma, lin bus pin recessive, (note 3) i bat v bat power-down current transceiver only ? 23 50 a cs/wake = high, voltage regulator disabled i ddq v reg quiescent operating current ?500 ? a (note 2) i vreg v reg maximum output current ?? 50 ma (note 4) microcontroller interface v ih high-level input voltage (txd, fault /slps) 2.0 ? v reg + 0.3 v v il low-level input voltage (txd, fault /slps) -0.3 ? 0.15 x v reg v i ihtxd high-level output current (txd) -90 ? +30 a input voltage = 4v i iltxd low-level output current (txd) -150 ? -10 a input voltage = 1v (though > 50 k ? internal pull-up) v ihcs / wake high-level input voltage (cs/wake) 3.0 ? v bat v through an external current- limiting resistor (10 k ? ) v ilcs / wake low-level input voltage (cs/wake) -0.3 ? 1.0 v i ihcs / wake high-level input current (cs/wake) -10 ? +80 a input voltage = 4v (though >100 k ? internal pull-down) i ilcs / wake low-level input current (cs/wake) 5 ? 30 a input voltage = 1v v ohrxd high-level output voltage (rxd) 0.8 v reg ?? i oh = -4 ma v olrxd low-level output voltage (rxd) ??0.2 v reg i ol = 4 ma bus interface v ihlbus high-level input voltage (l bus ) 0.6 v bat ? 18 v recessive state v illbus low-level input voltage (l bus ) -8 ? 0.4 v bat v dominant state v hys input hysteresis 0.05 v bat ? 0.1 v bat vv ih - v il note 1: internal current limited. 2.0 ms maximum recovery time (r lbus = 0 ? , tx = 0.4 v reg , v lbus = v bat ). 2: for design guidance only, not tested. 3: this current is at the v bat pin. 4: the maximum power dissipation is a function of t jmax , ja and ambient temperature t a . the maximum allowable power dissipation at an ambient temperature is p d = (t jmax - t a ) ja . if this dissipation is exceeded, the die temperature will rise above 150 c and the mcp201 will go into thermal shutdown. ? 2004 microchip technology inc. ds21730d-page 15 mcp201 i ol low-level output current (l bus ) 40 ? 200 ma output voltage = 0.1 v bat , v bat = 12v i o high-level output current (l bus ) -20 ? 20 a v bus v bat , v lbus < 40v i p pull-up current on input (l bus ) -180 ? -60 a approx. 30 k ? internal pull-up @ v ih = 0.7 v bat i sc short-circuit current-limit 50 ? 200 ma (note 1) v oh high-level output voltage (l bus ) 0.8 v bat ?? v v ol low-level output voltage (l bus ) ??0.2 v bat v 2.2 dc specifications (continued) dc specifications electrical characteristics: unless otherwise indicated, all limits are specified for: v bat = 6.0v to 18.0v t amb = -40c to +125c c loadreg = 10 f sym. parameter min. typ. max. units conditions note 1: internal current limited. 2.0 ms maximum recovery time (r lbus = 0 ? , tx = 0.4 v reg , v lbus = v bat ). 2: for design guidance only, not tested. 3: this current is at the v bat pin. 4: the maximum power dissipation is a function of t jmax , ja and ambient temperature t a . the maximum allowable power dissipation at an ambient temperature is p d = (t jmax - t a ) ja . if this dissipation is exceeded, the die temperature will rise above 150 c and the mcp201 will go into thermal shutdown. mcp201 ds21730d-page 16 ? 2004 microchip technology inc. voltage regulator v reg output voltage 4.75 ? 5.25 v 0 ma > i out > 50 ma, 7.0v < v bat < 18v v reg 1 output voltage 4.4 ? 5.25 v 0 ma > i out > 50 ma, 6.0v < v bat < 7.0v ? v reg 1 line regulation ? 10 50 mv i out = 1 ma, 7.0v < v bat < 18v ? v reg 2 load regulation ? 10 50 mv 5 ma < i out < 50 ma, v bat = constant v n output noise voltage ? ? 400 v rms 1v rms @ 10 hz - 100 khz v sd shutdown voltage (monitoring v reg ) 3.5 ? 4.0 v see figure 1-4 v on input voltage to turn on output (monitoring v bat ) 5.5 ? 6.0 v 2.2 dc specifications (continued) dc specifications electrical characteristics: unless otherwise indicated, all limits are specified for: v bat = 6.0v to 18.0v t amb = -40c to +125c c loadreg = 10 f sym. parameter min. typ. max. units conditions note 1: internal current limited. 2.0 ms maximum recovery time (r lbus = 0 ? , tx = 0.4 v reg , v lbus = v bat ). 2: for design guidance only, not tested. 3: this current is at the v bat pin. 4: the maximum power dissipation is a function of t jmax , ja and ambient temperature t a . the maximum allowable power dissipation at an ambient temperature is p d = (t jmax - t a ) ja . if this dissipation is exceeded, the die temperature will rise above 150 c and the mcp201 will go into thermal shutdown. ? 2004 microchip technology inc. ds21730d-page 17 mcp201 2.3 ac specifications table 2-1: mcp201 thermal specifications ac specifications electrical characteristics: unless otherwise indicated, all limits are specified for: v bat = 6.0v to 18.0v t amb = -40c to +125c symbol parameter min typical max units conditions bus interface |dv/dt| slope rising and falling edges 1.0 2.0 3.0 v/ s (40% to 60%), no load |dv/dt| slope rising and falling edges alternate 2.0 4.0 6.0 v/ s( note 1 ), no load t transpd propagation delay of transmitter ? ? 6.0 st recpd = max t recpd propagation delay of receiver ? ? 6.0 s(t recpdr or t recpdf ) t recsym symmetry of propagation delay of receiver rising edge with respect to falling edge -2.0 ? 2.0 st recsym = max t transsym symmetry of propagation delay of transmitter rising edge with respect to falling edge -2.0 ? 2.0 st transsym = max (t transpdf - t ranspdr ) voltage regulator t bactve bus activity to voltage regulator enabled 10 ? 40 s bus debounce time t vevr voltage regulator enabled to ready ?50200 s (note 2) t vregpo r voltage regulator enabled to ready after por ??2.5ms (note 2) c load = 25 nf t csor chip select to operation ready 0 50 200 s (note 2) t cspd chip select to power-down 0 ? 40 s (note 2) no c load t shutdown short-circuit to shutdown ? 450 ? s characterized but not tested t screc short-circuit recovery time ? 3.0 ? ms characterized but not tested note 1: the mode does not conform to lin bus specification version 1.3. 2: time depends on external capacitance and load. sym parameter min typical max units test conditions recovery recovery temperature (junction temperature) ?+135? c characterized but not tested shutdown shutdown temperature (junction temperature) ?+155? c characterized but not tested t therm thermal recovery time (after fault condition removed) ? 5.0 ? ms characterized but not tested mcp201 ds21730d-page 18 ? 2004 microchip technology inc. 2.4 timing diagrams and specifications figure 2-1: bus timing diagram figure 2-2: regulator timing diagram on cs/wake signal .6 v bat .4 v bat t transpdr t recpdr t transpdf t recpdf txd l bus rxd t cspd t csor cs/wake v reg regulator stable ? 2004 microchip technology inc. ds21730d-page 19 mcp201 figure 2-3: regulator timing diagram on bus activity figure 2-4: por diagram l bus .4 v bat t vevr t bactve v reg regulator stable v reg t vregpor v bat 6v 5.0v mcp201 ds21730d-page 20 ? 2004 microchip technology inc. 3.0 characterization graphs figure 3-1: i dd (ma) vs. v bat v bat (v) i dd (ma) vs. v bat i dd (ma) 0.65 0.6 0.55 0.5 0.45 0.4 0.35 0.3 4 6 8 101214161820 0.25 dap/jx 3/3/03 30 parts y1004 b2 txd = high v reg load = 0a i dd (ma) -40(c ) i dd (ma) (25c) i dd (ma) 125(c ) ? 2004 microchip technology inc. ds21730d-page 21 mcp201 figure 3-2: regulator voltage (v) vs. regulator current v regout (v) v bat 18(v) -40(c) v regout (v) v bat 14.4(v) -40(c) v regout (v) v bat 8(v) -40(c) v regout (v) v bat 6(v) -40(c) v regout (v) v bat 18(v) 25(c) v regout (v) v bat 14.4(v) 25(c) v regout (v) v bat 8(v) 25(c) v regout (v) v bat 6(v) 25(c) v regout (v) v bat 18(v) 125(c) v regout (v) v bat 14.4(v) 125(c) v regout (v) v bat 8(v) 125(c) v regout (v) v bat 6(v) 125(c) regulator voltage (v) regulator current (ma) 5.25 5.15 5.05 4.95 4.85 4.75 4.65 4.45 4.55 4.35 4.25 0 102030405060 dap/jx 2/28/03 30 parts y1004 b2 regulator voltage (v) vs. regulator current (a) mcp201 ds21730d-page 22 ? 2004 microchip technology inc. figure 3-3: regulator change (v) vs. line voltage change regulator change (mv) -40(c) load = 50(ma) regulator change (mv) -40(c) load = 25(ma) regulator change (mv) -40(c) load = 1(ma) regulator change (mv) 25(c) load = 25(ma) regulator change (mv) 125(c) load = 50(ma) regulator change (mv) 125(c) load = 25(ma) regulator change (mv) 125(c) load = 5(ma) regulator change (mv) 125(c) load = 1(ma) regulator change (mv) 25(c) load = 5(ma) regulator change (mv) 25(c) load = 1(ma) regulator change (mv) 25(c) load = 50(ma) regulator change (mv) -40(c) load = 5(ma) line regulation regulator change (v) vs line voltage change (mv) line voltage change (v) regulator change (mv) 5 0 -5 -10 -15 -20 -25 -30 -35 -40 0 2 4 6 8 10 12 14 dap/jx 3/3/03 30 parts y1004 b2 ? 2004 microchip technology inc. ds21730d-page 23 mcp201 figure 3-4: load regulation regulator change vs. regulator load change load regulation regulator change (mv) vs. regulator load change (ma) re g ular load current chan g e ( ma ) regular charge (mv) 0 102030405060 dap/jx 3/3/03 30 parts y1004 b2 regulator change (mv) -40c v bat = 14.4v regulator change (mv) 125c v bat = 18v regulator change (mv) 125c v bat = 14.4v regulator change (mv) 125c v bat = 8.0v regulator change (mv) 125c v bat = 6.0v regulator change (mv) 25c v bat = 6.0v regulator change (mv) 25c v bat = 8.0v regulator change (mv) 25c v bat = 14.4v regulator change (mv) 25c v bat = 18v regulator change (mv) -40c v bat = 6.0v regulator change (mv) -40c v bat = 8.0v regulator change (mv) -40c v bat = 18v 70 60 50 40 30 20 10 0 mcp201 ds21730d-page 24 ? 2004 microchip technology inc. figure 3-5: falling edge normal dv/dt vs. vbat falling edge normal dvdt (v/s) vs. v bat (v) falling edge normal dvdt (v/s) 2.40 2.35 2.30 2.25 2.20 2.15 2.10 2.05 2.00 1.95 1.90 4 6 8 10 12 14 16 18 20 falling edge normal dvdt (v/s) -40(c) falling edge normal dvdt (v/s) 25(c) falling edge normal dvdt (v/s) 125(c) v bat (v) dap/jx 3/6/03 30 parts y1004 b2 ? 2004 microchip technology inc. ds21730d-page 25 mcp201 figure 3-6: rising edge normal dv/dt vs. vbat rising edge normal dv/dt (v/s) vs. v bat (v) rising edge normal dv/dt (v/s) 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 4 6 8 101214161820 rising edge normal dvdt (v/s) -40(c) rising edge normal dvdt (v/s) 125(c) rising edge normal dvdt (v/s) 25(c) dap/jx 3/6/03 30 parts y1004 b2 v bat (v) mcp201 ds21730d-page 26 ? 2004 microchip technology inc. figure 3-7: bus active vs. vbat t bactive (s) vs. v bat (v) 20 18 16 14 12 10 8 6 4 30 35 40 45 50 55 tbactive (s) -40(c) tbactive (s) 25(c) tbactive (s) 125(c) dap/jx 3/6/03 30 parts y1004 b2 v bat (v) t bactive (s) ? 2004 microchip technology inc. ds21730d-page 27 mcp201 figure 3-8: voltage regulator active time vs. vbat t vevr (s) vs. v bat (v) t vevr (s) 10000 1000 100 10 4 6 8 10 12 14 16 18 20 10 t vevr (s) -40(c) t vevr (s) 25(c) t vevr (s) 125(c) v bat (v) dap/jx 3/6/03 30 parts y1004 b2 mcp201 ds21730d-page 28 ? 2004 microchip technology inc. figure 3-9: chip select to operation ready t csor (s) vs. v bat (v) t csor (s) 14 13 12 11 10 9 8 7 6 5 4 20 18 16 14 12 10 8 6 4 t csor (s) -40(c) t csor (s) 125(c) t csor (s) 25(c) v bat (v) dap/jx 3/5/03 30 parts y1004 b2 ? 2004 microchip technology inc. ds21730d-page 29 mcp201 figure 3-10: chip select to power down t cspd (s) vs. v bat (v) t cspd (s) 0 100 200 300 400 500 600 700 4 6 8 10 12 14 16 18 20 t cspd (s) -40(c) t cspd (s) 125(c) t cspd (s) 25(c) v bat (v) dap/jx 3/5/03 30 parts y1004 b2 mcp201 ds21730d-page 30 ? 2004 microchip technology inc. figure 3-11: propagation delay of transmitter t transpd (s) rising edge normal vs. v bat (v) 1.8 1.7 1.6 1.5 1.9 2 2.1 2.2 2.3 2.4 2.5 4 6 8 10 12 14 16 18 20 t transpd (s) rising edge normal -40(c) t transpd (s) rising edge normal 25(c) t transpd (s) rising edge normal 125(c) v bat (v) dap/jx 3/6/03 30 parts y1004 b2 t transpd (s) rising edge normal ? 2004 microchip technology inc. ds21730d-page 31 mcp201 figure 3-12: propagation delay of receiver t recpd (s) falling edge normal vs. v bat (v) 1.9 1.7 1.5 2.1 2.3 2.5 2.7 2.9 3.1 3.3 4 6 8 10 12 14 16 18 20 t recpd (s) falling edge normal -40(c) t recpd (s) falling edge normal 25(c) t recpd (s) falling edge normal 125(c) v bat (v) dap/jx 3/6/03 30 parts y1004 b2 t recpd (s) falling edge normal mcp201 ds21730d-page 32 ? 2004 microchip technology inc. notes: ? 2004 microchip technology inc. ds21730d-page 33 mcp201 4.0 packaging information 4.1 package marking information xxxxxxxx xxxxxnnn yyww 8-lead pdip (300 mil) example: 8-lead soic (150 mil) example: xxxxxxxx xxxxyyww nnn e/p256 0415 mcp201 e/sn0415 256 mcp201 legend: xx...x customer specific information* yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard device marking consists of microchip part number, year code, week code, and traceability code (facility code, mask rev#, and assembly code). for device marking beyond this, certain price adders apply. please check with your microchip sales office. 8-lead dfn-s example : xxxxxxxx xxxxxxxx yyww nnn mcp201 e/mf 0415 256 mcp201 ds21730d-page 34 ? 2004 microchip technology inc. 8-lead plastic dual flat no lead package (mf) 6x5 mm body (dfn-s) nom .050 bsc inches .194 bsc .184 bsc .226 bsc .236 bsc .008 ref. d overall width jedec equivalent: pending notes: drawing no. c04-113 molded package width lead width *controlling parameter mold draft angle top tie bar width lead length r b l d1 .014 .020 dimension limits molded package thickness pitch overall height overall length molded package length base thickness standoff number of pins a3 e1 e a2 a1 a .000 units n p min top view 12 a2 a 5.99 bsc .019 12 .030 .014 .016 .024 0.35 0.50 .356 0.40 0.60 5.74 bsc 12 0.47 0.75 millimeters* .039 .002 .031 .026 .0004 .033 0.00 8 max min 1.27 bsc 0.20 ref. 4.92 bsc 4.67 bsc 0.85 0.01 0.65 0.80 0.05 1.00 max nom 8 bottom view n e e1 pin 1 p b exposed pad length e2 exposed pad width d2 .085 .091 .097 2.16 2.31 2.46 .152 .158 .163 3.85 4.00 4.15 exposed metal pads d2 e2 a1 a3 l id d1 d r dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per si de. ? 2004 microchip technology inc. ds21730d-page 35 mcp201 8-lead plastic dual in-line (p) ? 300 mil (pdip) b1 b a1 a l a2 p e eb c e1 n d 1 2 units inches* millimeters dimension limits min nom max min nom max number of pins n 88 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .360 .373 .385 9.14 9.46 9.78 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top 51015 51015 mold draft angle bottom 51015 51015 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed jedec equivalent: ms-001 drawing no. c04-018 .010? (0.254mm) per side. significant characteristic mcp201 ds21730d-page 36 ? 2004 microchip technology inc. 8-lead plastic small outline (sn) ? narrow, 150 mil (soic) foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.33 .020 .017 .013 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 0.76 0.62 0.48 .030 .025 .019 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 5.00 4.90 4.80 .197 .193 .189 d overall length 3.99 3.91 3.71 .157 .154 .146 e1 molded package width 6.20 6.02 5.79 .244 .237 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n p b e e1 h l c 45 a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-012 drawing no. c04-057 significant characteristic ? 2004 microchip technology inc. draft ds21730d-page 37 mcp201 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . sales and support part no. x /xx package temperature range device device: mcp201: lin transceiver with voltage regulator mcp201t: lin transceiver with voltage regulator (tape and reel) temperature range: i = -40c to +85c e = -40c to +125c package: mf = dual flatpack, no-lead (6x5 mm body), 8-lead p = plastic dip (300 mil body), 8-lead sn = plastic soic, (150 mil body), 8-lead examples: a) mcp201-e/sn: extended temperature, soic package. b) mcp201-e/p: extended temperature, pdip package. c) mcp201-i/sn: industrial temperature, soic package. d) mcp201-i/p: industrial temperature, pdip package. e) mcp201t-i/sn: tape and reel, industrial temperature, soic package. f) mcp201t-e/sn: tape and reel, extended temperature, soic package. g) mcp201-e/mf: extended temperature, dfn package. h) mcp201t-e/mf: tape and reel, extended temperature, dfn package. data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recommended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. mcp201 ds21730d-page 38 draft ? 2004 microchip technology inc. notes: ? 2004 microchip technology inc. ds21730d-page 39 information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. no representation or warranty is given and no liability is assumed by microchip technol ogy incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of micr ochip?s products as critical components in life support syst ems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or ot herwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic, and smartshunt are registered trademarks of micr ochip technology incorporated in the u.s.a. and other countries. amplab, filterlab, mxdev, mxlab, picmaster, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, app lication maestro, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, migratable memory, mpasm, mplib, mplink, mpsim, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, rflab, rfpicdem, select mode, smart serial, smarttel and total endurance ar e trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2004, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona and mountain view, california in october 2003. the company?s quality system processes and procedures are for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. ds21730d-page 40 ? 2004 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: 480-792-7627 web address: www.microchip.com atlanta 3780 mansell road, suite 130 alpharetta, ga 30022 tel: 770-640-0034 fax: 770-640-0307 boston 2 lan drive, suite 120 westford, ma 01886 tel: 978-692-3848 fax: 978-692-3821 chicago 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas 16200 addison road, suite 255 addison plaza addison, tx 75001 tel: 972-818-7423 fax: 972-818-2924 detroit tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 kokomo 2767 s. albright road kokomo, in 46902 tel: 765-864-8360 fax: 765-864-8387 los angeles 25950 acero st., suite 200 mission viejo, ca 92691 tel: 949-462-9523 fax: 949-462-9608 san jose 1300 terra bella avenue mountain view, ca 94043 tel: 650-215-1444 fax: 650-961-0286 toronto 6285 northam drive, suite 108 mississauga, ontario l4v 1x5, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific australia microchip technology australia pty ltd unit 32 41 rawson street epping 2121, nsw sydney, australia tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing unit 706b wan tai bei hai bldg. no. 6 chaoyangmen bei str. beijing, 100027, china tel: 86-10-85282100 fax: 86-10-85282104 china - chengdu rm. 2401-2402, 24th floor, ming xing financial tower no. 88 tidu street chengdu 610016, china tel: 86-28-86766200 fax: 86-28-86766599 china - fuzhou unit 28f, world trade plaza no. 71 wusi road fuzhou 350001, china tel: 86-591-7503506 fax: 86-591-7503521 china - hong kong sar unit 901-6, tower 2, metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2401-1200 fax: 852-2401-3431 china - shanghai room 701, bldg. b far east international plaza no. 317 xian xia road shanghai, 200051 tel: 86-21-6275-5700 fax: 86-21-6275-5060 china - shenzhen rm. 1812, 18/f, building a, united plaza no. 5022 binhe road, futian district shenzhen 518033, china tel: 86-755-82901380 fax: 86-755-8295-1393 china - shunde room 401, hongjian building, no. 2 fengxiangnan road, ronggui town, shunde district, foshan city, guangdong 528303, china tel: 86-757-28395507 fax: 86-757-28395571 china - qingdao rm. b505a, fullhope plaza, no. 12 hong kong central rd. qingdao 266071, china tel: 86-532-5027355 fax: 86-532-5027205 india divyasree chambers 1 floor, wing a (a3/a4) no. 11, o?shaugnessey road bangalore, 560 025, india tel: 91-80-22290061 fax: 91-80-22290062 japan yusen shin yokohama building 10f 3-17-2, shin yokohama, kohoku-ku, yokohama, kanagawa, 222-0033, japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea 135-882 tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 singapore 200 middle road #07-02 prime centre singapore, 188980 tel: 65-6334-8870 fax: 65-6334-8850 taiwan kaohsiung branch 30f - 1 no. 8 min chuan 2nd road kaohsiung 806, taiwan tel: 886-7-536-4816 fax: 886-7-536-4817 taiwan taiwan branch 11f-3, no. 207 tung hua north road taipei, 105, taiwan tel: 886-2-2717-7175 fax: 886-2-2545-0139 taiwan taiwan branch 13f-3, no. 295, sec. 2, kung fu road hsinchu city 300, taiwan tel: 886-3-572-9526 fax: 886-3-572-6459 europe austria durisolstrasse 2 a-4600 wels austria tel: 43-7242-2244-399 fax: 43-7242-2244-393 denmark regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45-4420-9895 fax: 45-4420-9910 france parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany steinheilstrasse 10 d-85737 ismaning, germany tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy via salvatore quasimodo, 12 20025 legnano (mi) milan, italy tel: 39-0331-742611 fax: 39-0331-466781 netherlands waegenburghtplein 4 nl-5152 jr, drunen, netherlands tel: 31-416-690399 fax: 31-416-690340 united kingdom 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44-118-921-5869 fax: 44-118-921-5820 07/12/04 w orldwide s ales and s ervice |
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